View LV24010LP_1188959.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Ordering number : ENA0466
Bi-CMOS LSI
LV24010LP
Overview
Compact Portable Equipment
1-Chip FM+RDS Tuner IC
The LV24010LP is single-chip FM radio with RDS tuner IC that requires absolutely no external components. This design was achieved by combining Sanyo BiCMOS process technology, Sanyo packaging technology, and filtering circuit technology developed by Semiconductor Ideas to the Market (ItoM) B.V.
Functions
* FM FE. * FM IF. * MPX stereo decoder. * Tuning. * Standby. * RDS.
Specifications
Maximum Ratings at Ta = 25C
Parameter Maximum supply voltage Symbol VCC max VDD max Maximum input voltage VIN1 max VIN2 max Allowable power dissipation Storage temperature Operating temperature Pd max Tstg Topr Conditions Analog block supply voltage Digital block supply voltage Clock, Data, NR-W Extenal_clk_in Ta70C * Ratings 5.0 4.5 VDD+0.3 VDD+0.3 140 -40 to +125 -20 to +70 unit V V V V mW C C
*: With 40 x 50x 0.8mm3, glass epoxy substrate
Operating Conditions at Ta = 25C
Parameter Recommended supply voltage Symbol VCC VDD VCC op Operating supply voltage range VDD op VIO op Interface voltage Note: The application voltage of VIO to be used must be either equal to VDD or the VDD value or less (VIO VDD). Conditions Analog block supply voltage Digital block supply voltage Ratings 3.0 3.0 2.7 to 5.0 2.5 to 4.0 1.8 to 4.0 unit V V V V V
Any and all SANYO Semiconductor products described or contained herein do not have specifications
SANYO Semiconductor assumes no responsibility for equipment failures that result from using products
that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO Semiconductor representative nearest you before using any SANYO Semiconductor products described or contained herein in such applications. at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor products described or contained herein.
N2206 MS PC 20060921-S00002 / 71306 MS OT 20060529-S00004 No.A0466-1/18
LV24010LP
Electrical Characteristics at Ta = 25C, VCC = 3.0V, VDD = 3.0V, in the measuring circuit specified, Soft Mute/Stereo = off
Parameter Current drain (in operation) ICCD Current drain (in standby) ICCD FM receive band F_range ICCA Symbol ICCA Conditions Measurement at pin 23 with 60 dB input in the analog block, Monaural input Measurement at pins 27 and 40 with 60 dB input in the digital block Measurement at pin 23 in the standby mode of the analog block Measurement at pins 27 and 40 in the standby mode of the digital block. 76 108 MHz FM receive characteristics;MONO: fc = 80MHz,fm = 1kHz, 22.5kHzdev. Note that Soft_stereo,Soft_and mute functions are OFF. 3dB sensitivity Practical sensitivity 1 Practical sensitivity 2 (Reference) Demodulation output Channel balance Signal-to-noise ratio Total harmonic distortion 1(MONO) Total harmonic distortion 2(MONO) Field intensity display level Mute attenuation FS Mute-Att Input level at which FS1 changes to FS2 60dBV, pin 11 output 6 60 16 70 26 dB dB THD2 60dBV, pin 11 output, 75kHdev 1.3 3 % Vo CB S/N THD1 -3dB LS QS1 QS2 60dBV, 22.5kHzdev output standard, -3dB input -3dB. Input level with S/N = 30dB, Deemphasis = 75s SG open display Input level with S/N = 26dB, Deemphasis = 75s, SG terminal display 60dBV, pin 11 output 60dBV, pin 11 output / pin 12 output 60dBV, pin 11 output 60dBV, pin 11 output, 22.5kHdev 50 -2 48 70 0 58 0.4 1.5 110 2 mV dB dB % 1.25 10 17 13 20 dBV EMF dBV EMF V 3 30 A 3 30 A 0.2 0.4 0.8 mA Ratings min typ 15 max 19 unit mA
FM receive characteristics; STEREO: fc = 80MHz, fm = 1kHz, VIN = 60dBV, L+R = 30% (22.5kHz), Pilot = 10% (7.5kHzdev) Separation Total harmonic distortion (Main) RDS characteristics RDS_center frequency -3dB bandwidth fcen BW-3dB Adjustment accuracy of RDS_VCO DAC value. (Adjustment accuracy of free_run frequency) Bandwidth of BPF to 57KHZ Center frequency. Set Block4 register 06h of Bit3-2 (RDSBW) to "11" ( ) is not guarantee value. Just for Reference value RDS Current drain Irds RDS current value at RDS Enable/Disable 2 4 mA (3.0) 5.5 (7.0) kHz 56.5 57.0 57.5 kHz SEP THD-ST L-mod, pin 11 output / pin 12 output Main-mod (for L+R input), pin 11 / pin 12 output, IHF_BPF 20 35 0.6 1.8 dB %
The output level is set to the VOL = 14 when the block 2, register 09h of control register map has the bit 3,2,1,0 = "0010" In other cases: * The IF_OSC frequency must be adjust to 140kHz with DAC of block 1, register 05h. * The IF_CENTER set bit value (block 2, register 03h) applies to same DAC value of IF_OSC. * The IF_BW set bit value (block2, register 05h) applies to the setting of the value 65% of the IF_OSC set bit value. * The RDS_OSC frequency must be adjust to 114kHz with DAC of block 4, register 07h. * The RDS_FLTDAC (block 4, register 03h) set bit value applies to the setting of value 95% of RDS_OSC set bit value.
No.A0466-2/18
LV24010LP
Interface Block Allowable Operation Range at Ta = -20 to +70C, VSS = 0V
Parameter Supply voltage Digital block input Symbol VDD VIH VIL Digital block output IOL VOL Clock input operating frequency External clock operating frequency Note: External clock input (pin 31) allows also input of the sine wave signal. fclk_ext (Pin 31) clock frequency for external input 32k 14M Hz fclk High-level input voltage range Low-level input voltage range Output current at Low level Output voltage at Low level IOL = 2mA (Pin 29) clock frequency for 3wire_bus Conditions Ratings min 2.5 0.7VDD 0 2.0 0.6 0.7 typ max 4.0 VDD 0.6 unit V V V mA V MHz
Package Dimensions
unit : mm 3302A
Top View Bottom View 0.35 5.0 21 20 30
5.0
40 11 10 1 0.2 (0.7)
0.05 0 NOM
0.85max
SANYO : VQLP40(5.0X5.0)
(0.7)
0.4
0.35
31
No.A0466-3/18
LV24010LP
Block Diagram
No.A0466-4/18
LV24010LP
Pin Function
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pin name GND NC NC FM-ANT1 FM-ANT2 GND NC NC NC NC LINE-OUT-L LINE-OUT-R Package-GND Package-GND Package-GND Package-GND Package-GND Package-GND NC NC MPX NC VCC NC Vstabi. NC VDD NR_W DATA CLOCK CLK_IN NC Package-GND Package-GND Package-GND Package-GND Package-GND Package-GND NC VI/O Digital interface supply voltage GND for Package-shied GND for Package-shied GND for Package-shied GND for Package-shied GND for Package-shied GND for Package-shied Do not connect. Digital supply voltage Digital interface Read/Write Digital interface DATA Digital interface Clock Reference clock-source input for measurement Connect to GND if not used. Do not connect. Stabilizer voltage 2.7V Do not connect. Analog supply voltage Do not connect. MPX-signal output VCC-0.3V Do not connect. Radio Lch Line-output Radio Rch Line-output GND for Package-shied GND for Package-shied GND for Package-shied GND for Package-shied GND for Package-shied GND for Package-shied Do not connect. Do not connect. 1.2V 1.2V Antenna input Antenna GND GND (Analog and Digital GND) Do not connect. Do not connect. Do not connect. Do not connect. Connect to GND. Description GND (Analog and Digital GND) Do not connect. Do not connect. DC_bias Remark
No.A0466-5/18
LV24010LP
Timing Diagram
Write timing
Symbol tW tDL tHD tCH tCL Delay from command to data
Parameter
Ratings min 750 750 750 750 750 typ max
unit ns ns ns ns ns
Delay from data stable to data latch time Data Hold time Clock High-level time Clock Low-level time
Read timing
Symbol tW tSU THD
Parameter Delay from command to 1st data bit Data Setup time Data hold time
Ratings min 350 350 350 typ max
unit ns ns ns
External clock timing (Pin 31)
Symbol tCH tCL Clock High-level time Clock Low-level time
Parameter
Ratings min 35 35 typ max
unit ns ns
No.A0466-6/18
LV24010LP
Digital interface specification (Interface specification: reference)
(1) 3-wire bus (For communication line) Access to the LV24010 is done through the 3-wire bus:
CLOCK NR_W DATA Data strobe, input to the LV24010 Command (Write or read data), input to the LV24010 Bi-directional pin: input to the LV24010 when NR_W is high, output from the LV24010 when NR_W is low.
The LV24010 can be configured to generate interrupt through the DATA-line. When interrupt mode is selected, care should be taken that the DATA-line connection to the application micro-controller also supports interrupt. When the required timing window for frequency measurements is not generated by the application micro-controller, an external clock must be connected to CLK_IN pin of the LV24010 (2) Register map (For register map) The LV24020 registers are divided in 2 blocks:
Block 01h Block 02h Block 04h Status and measurement Radio Control RDS control
To access a register in a block, the block must be first selected by writing the block number to the BLK_SEL register. Block selection can be skipped for subsequent accesses to other registers in the same block. The mapping is as follows:
Block 01h Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 02h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 04h 01h 03h 04h 05h 06h 07h 08h 09h Register name CHIP_ID BLK_SEL MSRC_SEL FM_OSC SD_OSC IF_OSC CNT_CTRL NA IRQ_MSK FM_CAP CNT_L CNT_H CTRL_STAT RADIO_STAT IRQ_ID IRQ_OUT BLK_SEL RADIO_CTRL1 IF_CENTER NA IF_BW RADIO_CTRL2 RADIO_CTRL3 STEREO_CTRL AUDIO_CTRL1 AUDIO_CTRL2 PW_SCTRL BLK_SEL RDS_FLTDAC RDAT_L RDAT_H RDS_CTRL RDS_OSC NA RDS_INPS Access R W W W W W W W W R R R R R W W W W W W W W W W W W W W R R W W W RDS input setting IF Bandwidth Radio Control 2 Radio control 3 Stereo Control Audio Control 1 Audio Control 1 Power and soft control Access register 01h of block 1 DAC control for RDS filter Demodulated RDS data - low byte Demodulated RDS data - high byte RDS control DAC control for RDS PLL oscillator Interrupt mask CAP bank control for RF-frequency Counter value low byte Counter value high byte Control status Radio station status Interrupt identify Set Interrupt on DATA-line Access register 01h of block 1 Radio control 1 IF Center Frequency Chip identification Block Select Measure source select DAC control for FM-RF oscillator DAC control for stereo decoder oscillator DAC control for IF oscillator Counter control Operation
Registers with blank colum are not defined and should not be accessed.
No.A0466-7/18
LV24010LP
(3) Register description (For each register content) Block x, Register 01h - BLK_SEL - Block Select register (Write Only)
7 6 5 4 BN[7:0] bit 7-0: BN[7:0]: 8-bit block number. For LV24010, the following numbers are valid: 01h. 02h. 04h. Note: This register can be accessed from any block. 3 2 1 0
Block 1, Register 00h - CHIP_ID - Chip identify register (Read Only)
7 6 5 4 ID[7:0] bit 7-0: ID[7:0]: 8-bit chip ID. The following ID's are defined: 0Bh for LV24010. 3 2 1 0
Block 1, Register 02h - MSRC_SEL - Measurement Source Select Register (Write-only)
7 MSR_O bit 7: 6 AFC_LVL 5 AFC_SPD 4 Reserved 3 Reserved 2 MSS_SD 1 MSS_FM 0 MSS_IF
MSR_O: Output measure source to DATA-pin. 0 = Measuring source not available at DATA-pin (normal operation). 1 = Measuring source available at DATA-pin (test mode).
bit 6:
AFC_LVL: AFC trigger level. 0 = AFC is always active (trigger at 0dBV). 1 = AFC is only active when field strength is above 20dBV.
bit 5:
AFC_SPD: AFC speed. 0 = AFC adjusts with 3Hz speed. 1 = AFC adjusts with 8kHz speed (test mode).
bit 4: bit 3: bit 2:
Reserved: Must be programmed with 0. Reserved: Must be programmed with 0. MSS_SD: Stereo decoder oscillator measurement. 0 = Disable stereo decoder oscillator measurement. 1 = Enable stereo decoder oscillator measurement.
bit 1:
MSS_FM: FM RF oscillator measurement. 0 = Disable FM RF oscillator measurement. 1 = Enable FM RF oscillator measurement.
bit 0:
MSS_IF: IF oscillator measurement. 0 = Disable IF oscillator measurement. 1 = Enable IF oscillator measurement.
Note: - Only one of the measurement source MSS_xx bits may be set at a time. - The FM RF frequency is divided by 256 before it goes to the measuring circuitry.
Block 1, Register 03h - FM_OSC - FM RF Oscillator Register (Write-only)
7 6 5 4 FMOSC[7:0] bit 7-0: Note: - Positive DAC control (i.e. the frequency increases with the register's value). - See also FM_CAP register. FMOSC[7:0]: DAC value to control the FM RF oscillator (fine step) 3 2 1 0
No.A0466-8/18
LV24010LP
Block 1, Register 04h - SD_OSC - Stereo Decoder Oscillator Register (Write-only)
7 6 5 4 SDOSC[7:0] bit 7-0: SDOSC[7:0]: DAC value to control the stereo decoder oscillator. 3 2 1 0
Note: Positive DAC control (i.e. the frequency increases with the register's value)
Block 1, Register 05h - IF_OSC - IF Oscillator Register (Write-only)
7 6 5 4 IFOSC[7:0] bit 7-0: IFOSC[7:0]: DAC value to control the IF oscillator. 3 2 1 0
Note: Positive DAC control (i.e. the frequency increases with the register's value).
Block 1, Register 06h - CNT_CTRL - Counters Control Register (Write-only)
7 CNT1_CLR bit 7: 6 CTAB2 5 CTAB1 4 CTAB0 3 SWP_CNT_L 2 CNT_EN 1 CNT_SEL 0 CNT_SET
CNT1_CLR: Clear counter 1 bit. 0 = Normal mode. 1 = Clear and keep counter 1 in reset mode.
bit 6-4:
CTAB[2:0]: Tab select for counter 2 measuring interval bits. Value 000b 001b 010b 011b 100b 101b 110b 111b Dec. 0 1 2 3 4 5 6 7 Stop value Stop after 2 counts. Stop after 8 counts . Stop after 32 counts. Stop after 128 counts. Stop after 512 counts. Stop after 2048 counts. Stop after 8192 counts. Stop after 32768 counts.
bit 3:
SWP_CNT_L: Swap counter 1 and counter 2 bit (Active low). 0 = Clock source 1 to counter 2, clock source 2 to counter 1 (swapping) 1 = Clock source 1 to counter 1, clock source 2 to counter 2 (no swap)
bit 2:
CNT_EN: Enable the currently selected counter bit. 0 = Disable counter (stop counting). 1 = Enable counter (counting mode).
bit 1:
CNT_SEL: counter select bit. 0 = Select counter 1 for measurement. 1 = Select counter 2 for measurement.
bit 0:
CNT_SET: Set counters bit. 0 = Normal mode. 1 = Set both counter 1 and counter 2 to FFFFh and keep them set.
No.A0466-9/18
LV24010LP
Block 1, Register 08h - IRQ_MSK - Interrupt Mask Register (Write-only)
7 Reserved bit 7: bit 6: 6 IM_MS 5 Reserved 4 Reserved 3 IRQ_LVL 2 IM_AFC 1 IM_FS 0 IM_CNT2
Reserved: Must be programmed with 0. IM_MS: Mono/Stereo interrupt mask bit. 0 = Disable mono/stereo change interrupt. 1 = Enable mono/stereo change interrupt.
bit 5: bit 4: bit 3:
Reserved: Must be programmed with 0. Reserved: Must be programmed with 0. IRQ_LVL: Interrupt level select bit. 0 = Drive DATA-line from low to high when interrupt occurs (active high). 1 = Drive DATA-line from high to low when interrupt occurs (active low).
bit 2:
IM_AFC: AFC out of range interrupt mask bit. 0 = Disable AFC out of range interrupt. 1 = Enable AFC out of range interrupt.
bit 1:
IM_FS: Field strength change interrupt mask bit. 0 = Disable field strength change interrupt. 1 = Enable field strength change interrupt.
bit 0:
IM_CNT2: Counter 2 counting done interrupt mask bit. 0 = Disable counter 2 counting done interrupt. 1 = Enable counter 2 counting done interrupt.
Block 1, Register 09h - FM_CAP - FM RF Capacitor Bank Register (Write-only)
7 6 5 4 FMCAP[7:0] bit 7-0: Note: - 71/2 bit CAP value (Bit[7:6]: Combination 10b and 01b results in the same CAP-range). - Negative control: de RF frequency decreases when increasing the register's value. - See also FM_OSC register. FMCAP[7:0]: CAP bank value to control the FM RF frequency (coarse steps) 3 2 1 0
Block 1, Register 0Ah - CNT_L - Counter Value Low Register (Read-only)
7 6 5 4 CNT_LSB[7:0] bit 7-0: CNT_LSB[7:0]: Lower 8-bit value of the 16 bit counter 3 2 1 0
Block 1, Register 0Bh - CNT_H - Counter Value High Register (Read-only)
7 6 5 4 CNT_MSB[7:0] bit 7-0: CNT_MSB[7:0]: Upper 8-bit value of the 16 bit counter 3 2 1 0
Block 1, Register 0Ch - CTRL_STAT - Control Status Register (Read-only)
7 REV3 bit 7-4: bit 3-1: bit 1: 6 REV2 5 REV1 4 REV0 3 Reserved 2 Reserved 1 COV_FLG 0 AFC_FLG
REV[3:0]: should be read as 0Dh. Reserved[1:0]: should be read as all 1 COV_FLG: counter overflow flag. 0 = No overflow of the internal counter. 1 = The last counting loop causes overflow of the internal counter.
bit 0:
AFC_FLG: AFC out of range bit 0 = AFC is within control range. 1 = AFC is out of control range.
Note: - Reading this register will clear AFC, count 2 done interrupt. - COV_FLG is clear when CLR_CNT1 bit of CNT_CTRL register is high.
No.A0466-10/18
LV24010LP
Block 1, Register 0Dh - RADIO_STAT - Radio Station Status Register (Read-only)
7 RSS_MS bit 7: RSS_MS: Radio station mono/stereo state bit. 0 = Mono. 1 = Stereo. bit 6-0: RSS_FS[6:0]: Radio station field strength bits. 1111111b = Field strength less then 10dBV. 0111111b = Field strength between 10 to 20dBV. 0011111b = Field strength between 20 to 30dBV. 0001111b = Field strength between 30 to 40dBV. 0000111b = Field strength between 40 to 50dBV. 0000011b = Field strength between 50 to 60dBV. 0000001b = Field strength between 60 to 70dBV. 0000000b = Field strength above 70dBV. Note: Reading this register will clear field strength and mono/stereo interrupt. 6 5 4 3 RSS_FS 2 1 0
Block 1, Register 0Eh - IRQ_ID - Interrupt Identify Register (Read-only)
7 Reserved bit 7: bit 6: 6 II_RDS 5 II_CNT2 4 Reserved 3 II_AFC 2 Reserved 1 Reserved 0 II_FS_MS
Reserved: should be read as 1. II_RDS: RDS data available interrupt. 0 = No counting 2 counting done interrupt. 1 = Measuring with counter 2 is done.
bit 5:
II_CNT2: Counter 2 counting done flag. 0 = No counting 2 counting done interrupt. 1 = Measuring with counter 2 is done.
bit 4: bit 3:
Reserved: should be read as 0. II_AFC: AFC out of range interrupt bit. 0 = No AFC interrupt. 1 = AFC fails to hold the RF-frequency in range.
bit 2: bit 1: bit 0:
Reserved: should be read as 0. Reserved: should be read as 0. II_FS_MS: Field strength and Mono/stereo interrupt bit. 0 = No change in either the field strength or the mono/stereo mode. 1 = Change in field strength bits detected or mono/stereo mode has changed.
Block 1, Register 0Fh - IRQ_OUT - Set Interrupt Out Register (Write Only)
7 6 5 4 IRQO_VAL[7:0] bit 7-0: IRQO_VAL[7:0]: Write any value to this register will select the interrupt as output on the DATA-line of the LV24010 (the DATA-line can then be used as interrupt pin) 3 2 1 0
No.A0466-11/18
LV24010LP
Block 2, Register 02h - RADIO_CTRL1 - Radio Control 1 Register (Write-only)
7 EN_MEAS bit 7: 6 EN_AFC 5 Reserved 4 Reserved 3 DIR_AFC 2 RST_AFC 1 Reserved 0 Reserved
EN_MEAS: Enable measurement bit. 0 = Normal mode. 1 = Measurement mode.
bit 6:
EN_AFC: Enable AFC bit. 0 = Disable AFC. 1 = Enable AFC.
bit 5: bit 4: bit 3:
Reserved: should be written with 0. Reserved: should be written with 1. DIR_AFC: AFC direction bit . 0 = AFC normal direction. 1 = AFC reverse direction (for test purpose).
bit 2:
RST_AFC: Reset AFC bit. 0 = Normal operation. 1 = Reset AFC to the middle of the control range.
bit 1: bit 0:
Reserved: should be written with 1. Reserved: should be written with 1.
Block 2, Register 03h - IF_CENTER - IF Center Frequency Register (Write-only)
7 6 5 4 IFCOSC[7:0] bit 7-0: IFCENT[7:0]: Value for centering the IF frequency . 3 2 1 0
Block 2, Register 05h - IF_BW - IF Bandwidth Register (Write-only)
7 6 5 4 IFBW[7:0] Bit 7-0: IFBW[7:0]: Value for IF bandwidth. 3 2 1 0
Block 2, Register 06h - RADIO_CTRL2 - Radio Control 2 Register (Write-only)
7 VREF2 bit 7: 6 VREF 5 STABI_BP 4 IF_PM_L 3 Reserved 2 Reserved 1 AGCSP 0 AM_ANT_BSW
VREF2: VREF2 control bit. 0 = VREF2 is ON. 1 = VREF2 is OFF.
bit 6:
VREF: VREF control bit. 0 = VREF is ON. 1 = VREF is OFF.
bit 5:
STABI_BP: Stabi Bypass bit. 0 = Internal voltage is Vstabi (normal operation). 1 = Internal voltage is VCC (stabi bypassed).
bit 4:
IF_PM_L: IF PLL mute bit. 0 = IF PLL mute on (presetting IF mode). 1 = IF PLL mute off (normal operation mode).
bit 3: bit 2: bit 1:
Reserved: should be written with 0. Reserved: should be written with 0. AGCSP: AGC speed control bit. 0 = Normal speed. 1 = High speed.
Note: Turn on this bit will speed up the field strength measurement (fast tuning). bit 0: Reserved: should be written with 0.
No.A0466-12/18
LV24010LP
Block 2, Register 07h - RADIO_CTRL3 - Radio Control 3 Register (Write-only)
7 AGC_SLVL bit 7: 6 VOLSH 5 Reserved 4 AMUTE_L 3 SE_FM 2 Reserved 1 Reserved 0 Reserved
AGC_SLVL: AGC set level bit. This bit must be set to 1 for normal operation mode.
bit 6:
VOLSH: Volume level shift bit. 0 = Normal volume level. 1 = Increase volume of 12dB.
bit 5: bit 4:
Reserved: should be written with 0. AMUTE_L: Audio mute bit. 0 = Audio muted. 1 = Audio not muted.
bit 3:
SE_FM: FM radio select bit. 0 = Disable FM radio. 1 = Enable FM radio.
bit 2: bit 1: bit 0:
Reserved: should be written with 0. Reserved: should be written with 0. Reserved: should be written with 0.
Block 2, Register 08h - STEREO_CTRL - Stereo Control Register (Write-only)
7 FRCST bit 7: 6 5 FMCS[2:0] FRCST: Force stereo bit. 0 = Normal mode. 1 = Force stereo mode for test. bit 6-4: FMCS[2:0]: FM channel separation bits. 0...7 = FM channel separation level. bit 3: AUTOSSR: Auto stereo slew rate enable bit. 0 = Disable stereo auto slew rate. 1 = Enable stereo auto slew rate. bit 2: DELTA_TN: Delta tune bit. 0 = Decrease delta tune. 1 = Normal delta tune. bit 1: SD_PM: Stereo decoder PLL mute bit. 0 = Stereo decoder PLL not muted (normal operation). 1 = Stereo decoder PLL is muted (presetting mode). bit 0: ST_M: FM stereo/mono mode bit. 0 = Stereo mode. 1 = Mono mode. 4 3 AUTOSSR 2 DELTA_TN 1 SD_PM 0 ST_M
Block 2, Register 09h - AUDIO_CTRL1 - Audio Control 1 Register (Write-only)
7 Reserved bit 7-4: bit 3-0: 6 Reserved 5 Reserved 4 Reserved 3 2 VOL_LVL 1 0
Reserved: should be written with 0 VOL_LVL: volume level bits 1111b = Minimum volume level. 0000b = Maximum volume level. Each level is about 3dB volume adjustment.
No.A0466-13/18
LV24010LP
Block 2, Register 0Ah - AUDIO_CTRL2 - Audio Control 2 Register (Write-only)
7 Reserved bit 7-6: bit 5: 6 Reserved 5 DEEMP 4 Reserved 3 Reserved 2 Reserved 1 Reserved 0 Reserved
Reserved: should be written with 11b. DEEMP: De-emphasis bit. 0 = De-emphasis 50s. 1 = De-emphasis 75s.
bit 4-0:
Reserved: should be written with 00000b.
Block 2, Register 0Bh - PW_SCTRL - Power and Soft Control Register (Write-only)
7 6 SS_CTRL bit 7-5: SS_CTRL: Soft stereo control bits (8 levels). 000b = Minimal soft stereo (off). 111b = Maximal soft stereo level. bit 4-2: SM_CTRL: Soft audio mute bits (8 levels). 000b = Minimal audio mute (off). 111b = Maximal soft audio mute level. bit 1: bit 0: Reserved: should be written with 0. PW_RAD: Radio circuitry power bit. 0 = Radio circuitry is switched OFF. 1 = Switch radio circuitry ON. Note: PW_RAD is 0 at power up. 5 4 3 SM_CTRL 2 1 Reserved 0 PW_RAD
Block 4, Register 03h - RDS_FLTDAC - RDS Filter DAC Register (Write-only)
7 6 5 4 RFLTDAC[7:0] bit 7-0: RFLTDAC[7:0]: DAC value for RDS filter. 3 2 1 0
Note: This register should be programmed with 95% of the value of RDS_OSC register.
Block 4, Register 04h - RDAT_L - RDS Data Low Register (Read-only)
7 6 5 4 RD_L[7:0] bit 7-0: RD_L[7:0]: Low byte of the RDS data. 3 2 1 0
Note: bit 0 contains the first received bit.
Block 4, Register 05h - RDAT_H - RDS Data High Register (Read-only)
7 6 5 4 RD_L[7:0] bit 7-0: RD_H[7:0]: High byte of the RDS data. 3 2 1 0
Note: bit 0 contains the first received bit.
No.A0466-14/18
LV24010LP
Block 4, Register 06h - RDS_CTRL - RDS Control Register (Write-only)
7 RDS_EN_L bit 7: 6 RDS_PM 5 RDSLRG 4 RDSITG_L 3 RDSBW1 2 RDSBW0 1 RDCNT_EN 0 RDCNT_RS
RDS_EN_L: Enable RDS (active low). 0 = RDS is switched ON. 1 = RDS is switched OFF.
bit 6:
RDS_PM: RDS PLL mute bit. 0 = RDS PLL is un-muted (normal operation mode). 1 = RDS PLL is muted (calibration mode).
bit 5:
RDSLRG: RDS lock range. 0 = Normal lock range. 1 = Lock range x 2.
bit 4:
RDSITG_L: RDS integrator. 0 = Enable RDS integrator. 1 = Disable RDS integrator.
bit 3-2:
RDSBW[1:0]: RDS Band Width Bits. 00 = RDS Bandwidth is 2.5 kHz. 01 = RDS Bandwidth is 3.5 kHz. 10 = RDS Bandwidth is 4.5 kHz. 11 = RDS Bandwidth is 5.5 kHz.
bit 1:
RDCNT_EN: Enable RDS received bit counter. 0 = Disable RDS counter. 1 = Enable RDS counter (normal mode).
Note: The RDS received bit counter should be enabled when RDS is enabled. bit 0: RDCNT_RS: Reset RDS received bit counter. 0 = Reset is switched OFF (normal mode). 1 = Reset is switched ON. Note: Generate RDS counter reset by making this bit high then low. This will flush the received RDS data FIFO.
Block 4, Register 07h - RDS_OSC - RDS PLL Oscillator Register (Write-only)
7 6 5 4 RDOSC[7:0] bit 7-0: RDOSC[7:0]: DAC value for RDS PLL oscillator. 3 2 1 0
Note: Positive DAC control (i.e. the frequency increases with the register's value).
Block 4, Register 09h - RDS_INPS - RDS Input Setting Register (Write-only)
7 Reserved bit 7-4: bit 3: 6 Reserved 5 Reserved 4 Reserved 3 RGAIN 2 RVREF 1 MPXDIV 0 EN_RNH
Reserved: Must be programmed with 0000b. RDS_PM: RDS PLL mute bit. 0 = RDS PLL is un-muted (normal operation mode). 1 = RDS PLL is muted (calibration mode).
bit 5:
RGAIN: Gain control. 0 = 11 x. 1 = 8 x.
bit 2:
RVREF: Measure RDS Vref. 0 = Disable. 1 = Enable (test purpose only).
bit 1:
MPXDIV: MPX input divider. 0 =1:3. 1 =1:1.
bit 0:
EN_RNH: RDS notch. 0 = Disable. 1 = Enable.
No.A0466-15/18
LV24010LP
Measurement Circuit
Application Circuit Example
Note1: The vale of External Component is just reference. Please set most suitable value under actual operation. Note2: In case of necessary about BPF for FM_in, Please take Consideration of most suitable value. Note3: We recommend to put R1,R2,R3,R4 for interface between MPU and IC. Note4: Please put Capacitor between VDD and GND also, put Capacitor between VCC and GND as shown on application. Note5: In case of not using External Clock_in (pin31), Please tie to GND.
No.A0466-16/18
LV24010LP
Recommended LV24010LP's PCB Layout Conditions
PCB substrate
* This IC has an inductor for local oscillation on the bottom side of the package. To enable coverage of the receive frequency range of 76MHz to 108MHz (according to the receive frequency 1 specification), it is requested to arrange the GND layer as the first layer on the PCB_A face directly below the package bottom surface, as shown in the figure.
Recommended PCB substrate layout
IC substrate_LV24010LP
Recommended GND layer for PCB directly below IC
* For this SPL, the receive frequency is measured under above following conditions: * The X-value can be freely set between Min = 2.2mm and Max = 3.8mm (The X-value for Sanyo Demo Board is 3.4mm). * It is recommended to avoid provision of other wiring within 0.4mm from the lower layer of PCB_GND as much as possible.
No.A0466-17/18
LV24010LP
Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Semiconductor Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, of otherwise, without the prior written permission of SANYO Semiconductor Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO Semiconductor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of November, 2006. Specifications and information herein are subject to change without notice.
PS No.A0466-18/18

▲Up To Search▲

Price & Availability of LV24010LP

	To Download LV24010LP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .